This invention relates to a floating-point arithmetic circuit for performing floating-point arithmetic of first and second input data, each of which is represented by a floating-point representation.
A floating-point arithmetic circuit of the type described is used in performing floating-point arithmetic of first and second input data. Each of the first and the second input data is represented by a floating-point representation. The first and the second input data are composed of first and second exponent parts and first and second fraction parts. Each of the first and the second exponent parts is represented by an exponent number to power of an input cardinal number. The floating-point arithmetic circuit comprises a pre-normalizing unit, an arithmetic unit, and a post-normalizing unit. The pre-normalizing unit is supplied with the first and the second exponent parts and the first and the second fraction parts. The pre-normalizing unit carries out a pre-normalization operation on the first and the second exponent parts and the first and the second fraction parts to produce a maximum exponent part and first and second pre-normalized fraction parts. The maximum exponent part indicates a maximum of the first and the second exponent parts. The first pre-normalized fraction part is one of the first and the second fraction parts that corresponds to the maximum exponent part. The second pre-normalized fraction part is the other of the first and the second fraction parts which is given by a shift equal to an absolute value of a difference between the first and the second exponent parts. The arithmetic unit is supplied with the first and the second pre-normalized fraction parts. The arithmetic unit carries out an arithmetic operation on the first and the second pre-normalized fraction parts to produce an operated fraction part. The post-normalizing unit is supplied with the maximum exponent part and the operated fraction part. The post-normalizing unit carries out a post-normalization operation to produce a post-normalized exponent part and a post-normalized fraction part.
According to prior art, the input cardinal number is a predetermined cardinal number, for example, equal to two. The post-normalizing unit comprises a shift count calculating circuit, a shifter, and an adjusting circuit. The shift count calculating circuit is supplied with the operated fraction part for calculating a shift count for use in normalizing the operated fraction part. The shifter is connected to the shift count calculating circuit and supplied with the operated fraction part. The shifter left-shifts the operated fraction part on the basis of the shift count to produce a shifted fraction part as the post-normalized fraction part. That is, the operated fraction part consists of a plurality of bits arranged from a most significant bit to a least significant bit. The shifter shifts the operated fraction part towards the most significant bit on the basis of the shift count. The adjusting circuit is connected to the shift count calculating circuit and supplied with the maximum exponent part. The adjusting circuit adjusts the maximum exponent part by using the shift count to produce an adjusted exponent part as the post-normalized exponent part.
The shift count calculating circuit has a propagation delay time. When the input cardinal number is equal to two, the propagation delay time is longer than one machine cycle but shorter than two machine cycles. Therefore, it takes a long time to carry out the post-normalization operation by the post-normalizing unit. On the other hand, the propagation delay time is shorter than one machine cycle when the input cardinal number is equal to sixteen. In this event, it takes a short time to carry out the post-normalization operation by the post-normalizing unit. However, the floating-point arithmetic circuit comprising such a post-normalizing unit cannot deal with the input data where the input cardinal number is equal to two.